Input output controller having interface logic coupled to DMA controller and plurality of address lines for carrying control information to DMA agent

ABSTRACT

A computer system performs direct memory access (DMA) transfers according to a DMA transfer protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. A DMA agent, system memory, and a DMA controller are coupled to the bus. The DMA controller uses the electrical interface of the PCI bus to control a DMA transfer between system memory and the DMA agent. According to one embodiment, a system I/O controller is coupled between the DMA controller and the PCI bus. The system I/O controller passes DMA control information from the DMA controller to the DMA agent using the electrical interface of the PCI bus. The electrical interface of the PCI bus includes a plurality of address lines and a grant signal line coupled to the DMA agent, wherein the system that I/O controller transmits DMA control information to the DMA agent while asserting the grant signal line.

FIELD OF THE INVENTION

The present invention relates to computer bus protocols and moreparticularly to computer bus protocols for performing direct memoryaccess (DMA) transactions.

BACKGROUND OF THE INVENTION

One widely accepted system architecture for personal computers has beenthe "AT" system architecture. Prior computer systems incorporating theAT system architecture include system buses that implement either theIndustry Standard Architecture (ISA) bus or the Extended IndustryStandard Architecture (EISA) bus.

The ISA system architecture provides a Direct Memory Access (DMA)protocol that allows blocks of information to be exchanged between anInput/Output (I/O) device and system memory without unnecessarily tyingup the resources of the system processor. Wherein the processorinitiates DMA transfers, a DMA controller actually manages DMAtransfers. When a DMA transfer is complete, the I/O device produces aninterrupt to inform the processor. The EISA system architecture is fullycompatible with the ISA DMA protocol, but the EISA system architecturealso provides enhanced DMA functions. Both the ISA and EISA systemarchitecture's provide multiple DMA "channels," wherein each DMA channelis assigned to a particular I/O device.

A more recent bus architecture is the Peripheral Component Interconnect(PCI) Local Bus architecture. As described by the PCI Local BusSpecification, Revision 2.0 (1993), the PCI Local Bus is a highperformance bus that is intended as an interconnect mechanism betweenhighly integrated peripheral controller components, peripheral add-inboards, and processor/memory subsystems.

The PCI Local Bus does not, itself, provide a DMA transfer mechanism.Instead, a computer system that incorporates the PCI Local Busarchitecture typically relies on the DMA services of an ISA or EISA busthat is coupled to the PCI Local Bus via a PCI-to-ISA/EISA bus bridge.The bus bridge typically includes a DMA controller that arbitrates DMArequests of local I/O devices coupled to the ISA or EISA bus. Once theDMA controller determines which DMA channel is to be serviced, the busbridge, as a PCI agent, arbitrates for control of the PCI bus to gainaccess to system memory and initiate the DMA transfer.

Modern personal computer systems, including mobile computer systems suchas laptops, are increasingly incorporating the PCI system architecture.Because of size constraints, mobile computer systems that incorporateboth the PCI and ISA/EISA architectures typically do not includeISA/EISA expansion slots. To increase the functionality of a mobilecomputer system in a desktop environment, many mobile computer systemmanufacturers provide an optional docking station to which the mobilecomputer system can be coupled via a PCI-to-PCI bus bridge. A dockingstation may include ISA/EISA expansion slots that allow for ISA/EISAadd-in boards, and it would be desirable to provide a mechanism to allowISA/EISA DMA agents of a docking station to utilize the DMA services ofthe mobile computer system.

SUMMARY AND OBJECTS OF THE INVENTION

Therefore, an object of the present invention is to provide a mechanismthat allows DMA transfers to be accomplished using the electricalinterface of a PCI local bus.

This and other objects of the invention are provided by a computersystem that performs direct memory access (DMA) transfers according to aDMA transfer protocol. The computer system may comprise a PeripheralComponent Interconnect (PCI) bus that includes an electrical interfaceas specified by a PCI Local Bus standard. A DMA agent, system memory,and a DMA controller are coupled to the bus. The DMA controller uses theelectrical interface of the PCI bus to control a DMA transfer betweensystem memory and the DMA agent. According to one embodiment, a systemI/O controller is coupled between the DMA controller and the PCI bus.The system I/O controller passes DMA control information from the DMAcontroller to the DMA agent using the electrical interface of the PCIbus. The electrical interface of the PCI bus includes a plurality ofaddress lines and a grant signal line coupled to the DMA agent, whereinthe system I/O controller transmits DMA control information to the DMAagent while asserting the grant signal line.

Other objects, features, and advantages of the present invention will beapparent from the accompanying drawings and from the detaileddescription which follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements, and in which:

FIG. 1 shows a computer system according to one embodiment.

FIG. 2 shows a system I/O controller according to one embodiment.

FIG. 3 shows a DMA expansion agent of the primary bus as includingsecondary arbiter.

FIG. 4 shows REQ#/GNT# control registers.

FIG. 5 shows a decoding of the values stored by the REQ#/GNT# controlregisters of FIG. 4.

FIG. 6 is a timing diagram showing a serial channel passing protocolwherein multiple channel requests are passed in single request cycle.

FIG. 7 is a flow chart showing a method for passing multiple requests.

FIG. 8 is a flow chart showing a method for passing multiple requestswhen, a formerly active request becomes inactive.

FIG. 9 is flow chart showing a method for passing multiple requests whena new request becomes active after the DMA expansion agent haspreviously passed its active requests.

FIG. 10 is a timing diagram showing a serial channel passing protocolwherein a single channel request is passed in single request cycle.

FIG. 11 shows a prior art PCI read transaction.

FIG. 12 shows a prior art PCI write transaction.

FIG. 13 shows the encoding of control information during the I/O phaseof a DMA transfer according to one embodiment.

FIG. 14 shows the byte alignment of DMA agents according to oneembodiment.

FIG. 15 shows the encoding of the byte enable lines when DMA agents arealigned as shown in FIG. 14.

FIG. 16 shows a complete DMA write transfer according to one embodiment.

DETAILED DESCRIPTION

As described herein, DMA services are provided for the bus agents of aprimary bus, and the DMA protocols described below may be implemented bya primary bus that operates according to the PCI Local Bus standard(revision 1.0 or later) without requiring changes to the electricalinterfaces of the bus agents or the primary bus. The primary busincludes a system I/O controller to which are coupled a set of requestsignal lines and a set of grant signal lines, wherein each requestsignal line and each grant signal line is coupled to a corresponding oneof the bus agents.

To request a DMA access, a bus agent simply asserts its request signalline in the appropriate manner. For example, a bus agent may assert anddeassert its request line over multiple clock cycles to indicate the DMAchannel or channels that it is requesting. Alternatively, the system I/Ocontroller may be configured to recognize any request of a particularbus agent as necessarily being a DMA request. DMA requests are passed toa DMA controller that arbitrates the DMA requests. Non-DMA requests arepassed to a primary bus arbiter. The DMA controller grants a DMA channelto a requesting bus agent, and this grant is passed to the requestingagent by the system I/O controller, which indicates a grant of a DMArequest by appropriately asserting the correct grant signal line.

When a DMA request is granted, the DMA controller becomes the bus masterof the primary bus and controls the DMA transfer between system memoryand the requesting bus agent. Each DMA write or read transfer includesan I/O phase, wherein data is read from or written to a bus agent, and amemory phase, wherein data is written to or read from system memory.During the I/O phase of a DMA transfer, the DMA controller uses theaddress lines of the primary bus to transfer codes to the bus agent thatindicate the type of DMA transfer that is to occur. The value of thecodes are chosen to correspond to the address space of the DMAcontroller to prevent bus agents that are not involved in the DMAtransfer from mistakenly recognizing that they are being addressed.

System Overview

FIG. 1 shows a mobile computer system 10 that may be coupled to adocking station 90. Mobile computer system 10 includes a hostbridge/memory controller 20, a system I/O controller 25, an enhancedcapabilities port (ECP) 30, a PC card controller 35, a graphicscontroller 40, a super I/O device 45, and a docking bus bridge 95, allof which are "primary bus agents" coupled to primary bus 15. When aprimary bus agent has data to transfer, the primary bus agent issues arequest. System I/O controller 25 includes a primary bus arbiter (asshown in FIG. 2) for determining which requesting primary bus agent isto be the "primary bus master" for a particular transaction. Variousother types of primary bus agents may be coupled to primary bus 15, andmobile computer system may alternatively be a desktop computer.

Mobile computer system 10 further includes a processor 50, a cache 55,system memory 60, display device 75, and secondary bus agents 65, 70,80, and 85. Docking station 90 is shown as including a secondary bus 100to which a secondary bus agent 105 and an expansion bus bridge 110 arecoupled as agents. The expansion bus bridge 110 is also coupled to anexpansion bus 115, to which are coupled expansion bus agents 120 and125.

Processor 50 and cache 55 are both coupled to a host bus 52, and hostbridge/memory controller 20 provides a data path from the host bus 52 tothe primary bus 15 and to system memory 60, which is coupled to a memorybus 62. Graphics controller 40 receives graphics information from systemmemory 60 via primary bus 15 for delivery to display device 75.

According to the present embodiment, primary bus 15 operates accordingto the PCI local bus standard (revision 1.0 or later), and each primarybus agent coupled to primary bus 15 includes a unique request signalline (REQ#) for requesting control of primary bus 15 from the primarybus arbiter. Each primary bus agent also includes a unique grant signalline (GNT#) that the primary bus arbiter uses to signal that the primarybus agent has been granted control of the primary bus. The REQ#/GNT#signal pair of each primary bus agent is coupled to the primary busarbiter. Wherein primary bus 15 is described as operating according tothe PCI Local Bus standard, the methods and apparatus described hereinmay be used in any bus system that provides unique request and grantsignal lines for each bus agent.

Primary bus agents that may request DMA accesses are generally referredto as "DMA agents." As will be described, some primary bus agents mayrequest access to multiple DMA channels, and such bus agents arereferred to as "DMA expansion agents." DMA expansion agents are providedbecause primary bus agents that are coupled to the secondary bus may becoupled to multiple devices that each may request a DMA channel. In FIG.1, each DMA agent and DMA expansion agent of primary bus 15 is labeled"DMA" in parentheses.

ECP 30, PC card controller 35, super I/O device 45, and docking busbridge 95 are each shown as being DMA agents of primary bus 15. ECP 30is a parallel port that directly controls a single DMA channel throughits REQ#/GNT# signal pair. PC card controller 35 may be a CardBuscontroller or PCMCIA card controller that indirectly controls multipleDMA channels. Super I/O 45 and docking bus bridge 95 are also DMAexpansion agents that may request multiple DMA channels.

Each DMA expansion agent is coupled to a secondary bus. For example, PCcard controller 35 is coupled to a secondary bus 37, and super I/O 45 iscoupled to secondary bus 47. When mobile computer system 10 is coupledto docking station 90, docking bus bridge 95 is coupled to secondary bus100, which may operate according to the PCI Local Bus standard. Multipledevices may be coupled to each of the secondary buses, and eachsecondary bus agent may request a DMA channel. For example, secondarybus agents 65 and 70 are coupled to secondary bus 37, secondary busagents 80 and 85 are coupled to secondary bus 47, and secondary busagent 105 and expansion bus bridge 110 are coupled to secondary bus 100.Each of the secondary bus agents 65 and 70 coupled to secondary bus 37may be a PC card that operates according to a PC card standard such asthe PCMCIA or CardBus standards. Secondary bus 47 may operate accordingto the ISA or EISA bus standards, and each of the secondary bus agents80 and 85 may be ISA or EISA I/O devices such as disk drives or inputdevices.

Each DMA expansion agent includes a secondary bus arbiter (as discussedwith respect to FIG. 3) that receives DMA requests from secondary busagents. The DMA expansion agent forwards received DMA requests to systemI/O controller 25 by asserting its REQ# line in a manner such as thatdescribed below with respect to FIG. 6.

FIG. 2 shows system I/O controller 25 as including primary bus arbiter130, primary bus interface logic 131, encode/decode logic 132, DMAcontroller 135, and buffer 137. DMA controller 135 may be alternativelylocated elsewhere, and DMA controller 135 is shown as being included insystem I/O controller 25 to facilitate discussion of the presentembodiments. Primary bus interface logic 131 and encode/decode logic132, provide the electrical interface to primary bus 15. Signal linedesignations ending in a pound sign ("#") indicate a signal that isasserted by placing the signal line in a logic low state. As describedabove, primary bus 15 may operate according to the PCI Local Busstandard. Therefore, encode/decode logic 132 is shown as being coupledto the arbitration lines REQn# and GNTn#, and primary bus interfacelogic 131 is shown as being coupled to multiplexed address/data lines AD31:0!, and to primary bus control signal lines FRAME#, TRDY#, IRDY#,C/BE# 3:0!. These signals and other signals of the PCI interface aredescribed in more detail in the PCI Local Bus standard. Each primary busagent that is capable of being a primary bus master includes anelectrical interface coupled to the same signals.

Encode/decode logic 132, which may be implemented as software orhardware, is provided to determine whether a primary bus requestreceived via the REQn# signal lines of primary bus 15 is to be forwardeddirectly to primary bus arbiter 130 via local REQn# signal lines orwhether the primary bus request is to be forwarded as a DMA request toDMA controller 135 via DMA request lines DREQn#. Primary bus arbiter 130arbitrates and grants normal primary bus master requests by assertingthe appropriate local GNTn# signal line, and encode/decode logic 132asserts the corresponding GNT# signal line in the appropriate manner toindicate a grant.

DMA controller 135 arbitrates DMA requests received via the DREQn#signal lines, and asserts the HOLD signal line to indicate a DMA requestis to be asserted. The HOLD signal line is coupled to primary busarbiter 130, which asserts the HLDA signal to acknowledge assertion ofthe HOLD signal and to provide bus mastership to DMA controller 135. DMAcontroller 135 asserts the appropriate DACKn# signal line in response toreceiving the HLDA signal, and encode/decode logic 132 appropriatelyasserts the correct GNTn# signal line.

DMA controller 135 may be implemented using the 8237 DMA controller chipsold by Intel Corporation of Santa Clara, Calif. As already has beendescribed, the electrical interface of the 8237 chip includes multipleDMA request lines DREQn# and multiple DMA acknowledge lines DACKn#.

The electrical interface between DMA controller 135 and primary businterface logic 131 is shown as including the control signals MRDC#,MWTC#, IORC#, IOWC#, and TC. DMA controller 135 asserts MRDC# toindicate a memory read operation; DMA controller 135 asserts MWTC# toindicate a memory write operation; DMA controller 135 asserts IORC# toindicate an I/O read command; DMA controller 135 asserts IOWC# toindicate an I/O write command; and DMA controller 135 asserts TC toindicate the last portion of data to be transferred (terminal count).For typical ISA/EISA systems, these control signals would be routeddirectly to the ISA/EISA bus agents or the processor. As describedbelow, primary bus interface logic 131 responds to the assertion of thecontrol signals by performing the primary bus transactions required toaccomplish a DMA transfer. DMA controller 135 may be provided withprimary bus interface logic that is distinct from the interface logic ofsystem I/O controller 25.

DMA controller 135 may also include a set of secondary bus address linesand data lines for the case wherein the DMA controller is coupleddirectly to a secondary bus. For example, according to one embodiment,DMA controller 135 may be incorporated in the circuitry of super I/Odevice 45, which is coupled to secondary bus 47. The control signalsoutput by DMA controller 135 may also be directly coupled to secondarybus agents. DMA controller 135 may therefore be used to directly receiveand grant DMA requests of local secondary bus agents without routinglocal DMA requests and grants through system I/O controller 25.

As will be described, DMA read and write transfers include one or moreread transactions (load) followed by one or more write transactions(store). Data buffer 137 may be provided to buffer data during DMAtransfers. For example, for the case of a DMA write transfer from aprimary bus agent to system memory, the data width of the primary busagent may be less then the width of the data bus. To reduce the numberof memory writes, it is desirable to perform two or more successive I/Oreads to obtain enough data to fill the data bus for the memory write.For example, the data width of the primary bus agent may be only sixteenbits, wherein the data bus width is thirty-two bits. Assuming that theprimary bus agent has at least thirty-two bits of data to transfer tomemory, the data may be transferred by performing a first 16-bit I/Oread and a first 16-bit memory write followed by a second 16-bit I/Oread and a second 16-bit memory write, and no buffering is required. Amore economical method of transferring thirty-two bits of data is toperform two successive 16-bit I/O reads followed by a single 32-bitmemory write. During a DMA read transfer, the data of a 32-bit memoryread may be buffered and sequentially outputted using two successive16-bit I/O write transactions.

Depending on the manner in which data is delivered to primary bus 15 bya primary bus agent, data buffer 137 may include logic for shiftingbuffered data so that it is properly aligned during the "store"portionof a DMA transfer. For example, each of the two 16-bit I/O readtransactions may assert the same sixteen data lines, 0 to 15. During the32-bit memory write transaction, all thirty-two data lines must beappropriately asserted. Therefore, the sixteen bits of data buffered forthe first 16-bit I/O read transaction are shifted to bit positions16-31, and the sixteen bits of data for the second I/O read transactionare stored in bit positions 0-15.

According to the present embodiment, a primary bus agent may request oneor more DMA channels by asserting its REQ# signal in an appropriatemanner, as described below. Encode/decode logic 132 is configured torecognize a DMA request and to forward DMA requests to DMA controller135 by asserting the corresponding DMA request signal line or linesDREQ#. DMA controller 135 arbitrates DMA requests and asserts the HOLDsignal. When DMA controller 135 receives the HLDA signal, it asserts theappropriate DMA acknowledge signal line DACK#. Encode/decode logic 132detects the assertion of a DACK# signal and asserts the GNT# signal lineof the primary bus agent requesting the DMA channel.

FIG. 3 shows the structure of a DMA expansion agent such as super I/Odevice 45. As shown, a DMA expansion agent may include a secondaryarbiter 140 that is coupled to received DMA requests from secondary busagents via local DREQ# signal lines. A DMA expansion agent may alsogenerate normal bus master requests.

The secondary bus arbiter 140 of a DMA expansion agent does notarbitrate DMA requests received from secondary bus agents. Instead,secondary bus arbiter 140 passes DMA requests to system I/O controller25 by appropriately asserting its REQ# signal line. When a grant isreceived via the GNT# signal line, the secondary arbiter 140 asserts theappropriate local DMA acknowledge line DACK#.

As will be described with respect to FIGS. 7-9, it is important for theDMA expansion agent to pass all currently active requests to the systemI/O controller 25. According to the present embodiment certain rules areimplemented to ensure that all active requests are serviced and that anyrequests previously asserted that subsequently become inactive are notserviced.

DMA Request Signaling Mechanisms And Protocols

The request/grant signal pairs of primary bus 15 may be used to requestand grant DMA transfer requests. Primary bus agents arbitrate forprimary bus 15 using their request/grant signal pairs, and eacharbitration transaction may be divided into a request phase and a grantphase. During the request phase, a primary bus agent issues its requestor requests using its request signal, and the primary bus arbiter or DMAcontroller arbitrates the requests. During the grant phase, theencode/decode logic passes a grant to a primary bus agent from eitherthe primary bus arbiter or the DMA controller by asserting theappropriate grant signal line.

Different mechanisms may be used to request and grant DMA transferrequests. For example, for DMA agents that may only request a single DMAchannel, encode/decode logic 132 may include a control registerindicating the DMA channel that the DMA agent may request. Thus,encode/decode logic 132 recognizes a DMA request whenever the REQ#signal of that DMA agent is asserted. Alternatively, a DMA agent mayindicate the DMA channel it is requesting by serially asserting anddeasserting its REQ# signal in a prescribed manner within a providedwindow of time. If each DMA agent may request only one DMA channel, itis sufficient to encode the channel request. For example, if eight DMAchannels are provided, three bus clock cycles may be provided duringwhich time the DMA agent encodes its DMA channel request byappropriately asserting and deasserting the REQ# signal line. For DMAexpansion agents that can request access to multiple DMA channels, theDMA channel request are not encoded so that multiple DMA channelrequests may be passed together. For example, if eight DMA channels areprovided, eight bus clock cycles that each correspond to a particularDMA channel may be provided. If the DMA expansion agent has a requestfor a particular DMA channel, the DMA expansion agent deasserts the REQ#signal for the corresponding clock cycle.

According to the present embodiment, encode/decode logic 132 includes aREQ#/GNT# control register for each bus agent that may be coupled toprimary bus 15. Each REQ#/GNT# control register indicates whether theparticular primary bus agent is a normal bus agent, a DMA agent, or aDMA expansion agent.

FIG. 4 shows a set of REQ#/GNT# control registers 145. Each controlregister 145 is a 4-bit register comprising a 3-bit channel field and a1-bit expansion field. A DMA expansion agent is signified by setting theexpansion bit of a control register to a logic one value. When theexpansion bit is set to a logic zero, the channel field signifies whichof eight "channels"--seven DMA channels and one bus master "channel"--iscontrolled by the primary bus agent. If the primary bus agent isassigned a bus master channel, the primary bus agent is a normal busagent and does not request DMA accesses.

When the REQ# of a primary bus agent is asserted, encode/decode logic132 scans the contents of the corresponding control register 145. If thecontrol register 145 indicates that the primary bus agent is requestingaccess as a primary bus master, encode/decode logic 132 arbitrates therequest normally. If the control register 145 indicates that the primarybus agent is a DMA agent, encode/decode logic 132 passes the request toDMA controller 135, which arbitrates DMA requests.

FIG. 5 shows one possible decoding for the contents of control registers145. When the expansion bit is at a logic low level, the three bits ofthe channel field indicate the primary bus agent as being either a DMAagent or a normal bus agent. For example, if the binary value of thechannel field is "001," the bus agent that is coupled to thecorresponding REQ#/GNT# signal pair is a DMA agent that requests DMAchannel 1. If the binary value of the channel field is "100," the busagent that is coupled to the corresponding REQ#/GNT# signal pair is anormal bus master that requests a normal bus master access.

If the expansion bit is at a logic high level, the primary bus agent isa DMA expansion agent, and the bits of the channel field are "don'tcares." The DMA expansion agent may request multiple DMA channels andnormal bus master access by asserting its REQ# signal line according toa serial channel passing protocol such as that described with respect toFIG. 6.

FIG. 6 is a timing diagram showing one serial channel passing protocolwherein a DMA expansion agent uses its REQ# signal line to pass multipleDMA requests to encode/decode logic 132 during a single request phase ofan arbitration transaction. The serial channel passing protocol shown inFIG. 6 enables a DMA expansion agent to request multiple DMA channels ina single request phase by serially toggling the REQ# line. As shown,nine clock cycles are provided to serially pass multiple channelrequests by a DMA expansion agent. A clock cycle is provided for each ofthe eight channels that may be requested, wherein the channel decode isthat described with respect to FIG. 5.

Upon the start of a serial channel request, the REQ# signal is assertedactive low for one full clock cycle. After the first clock cycle thereis a single clock cycle devoted to each channel that may be requested.More or fewer clock cycles may be required, depending on the number ofDMA channels implemented by a computer system. If the DMA expansionagent has an active request for a DMA channel, the DMA expansion agentdeasserts the REQ# signal during the clock cycle associated with the DMAchannel having the request. If a DMA expansion agent has multiple activeDMA requests, the DMA expansion agent deasserts the REQ# signal duringeach corresponding clock cycle. If a DMA expansion agent is requestingaccess as a primary bus master, the DMA expansion agent deasserts theREQ# signal during the clock cycle corresponding to channel 4. The REQ#of the requesting DMA expansion agent remains asserted while the DMAexpansion agent has a pending request.

Encode/decode logic 132 responds to the serially received request orrequests by passing on the DMA channel requests to DMA controller 135and by passing normal bus master requests to primary bus arbiter 130 fornormal arbitration for a bus master request. Encode/decode logic 132passes DMA requests to DMA controller 135 by asserting the DREQ# signalof each requested DMA channel. DMA controller 135 arbitrates the DMArequests and grants a DMA request by asserting the HOLD signal and theappropriate DACK# signal. Encode/decode logic 132 passes the grant ofthe DMA request to the appropriate DMA expansion agent by encoding thenumber of the granted channel on the GNT# signal line as shown in FIG.6. Four clock cycles are therefore used to serially provide a grant tothe requesting DMA expansion agent. After the first clock cycle, each ofthe three subsequent clock cycles corresponds to a bit of the channelfield, indicating which of the eight channels has been granted to theDMA expansion agents.

Each requesting secondary DMA bus agent is typically provided with atime-out mechanism that specifies a maximum amount of time is allowedfor a DMA request to complete. The time-out timer begins as soon as thesecondary bus agent makes the request, and it is imperative to provideeach DMA request to the DMA controller as soon as possible. Therefore,all active requests of a DMA expansion agent should be sent together, ifpossible. Sometimes, however, a request may become active after arequest has already been passed to encode/decode logic 132. Similarly, arequest may go inactive after it has already been passed toencode/decode logic 132.

The present embodiment implements a protocol regarding the handling ofmultiple active requests by DMA expansion agents. The rules of theprotocol may be synopsized as follows:

1) a DMA expansion agent having an outstanding request (wherein REQ# isasserted and a grant has not been received) drives its REQ# signal lineinactive for one clock cycle to signal new request information; and

2) a DMA expansion agent, upon completing one of multiple activerequests, drives its REQ# signal line inactive for two clock cyclesbefore signaling its remaining requests.

The rules implemented by the present embodiment presume that the REQ#and GNT# state machines of each primary bus agent run independently andconcurrently such that grants can be received while requests are made,and vice versa. The rules practiced by the present embodiment are chosenfor the specific implementation, and are not exhaustive of the ways inwhich the situations described below with respect to FIG. 7-9 may beprocessed by a DMA expansion agent.

FIG. 7 is a flow chart showing a general process for the handling ofmultiple active requests by a DMA expansion agent. At process block 700,a DMA expansion agent such as super I/O device 45 signals that it hasmultiple active requests using the serial signal and protocol shown inFIG. 6. For example, the DMA expansion agent may have active requestsfor channel 1 (DMA channel 1) and for channel 4 (a normal bus masteraccess). At process block 705, encode/decode logic 132 provides a grantof one of the requests, as shown in FIG. 6, in response to DMAcontroller 135. For example, primary arbiter 130 grants the DMAexpansion agent's request for channel 4 (normal bus master), andencode/decode logic 132 passes the grant. The first transactioncompletes at process block 710, at which time the DMA expansion agentstill has an active request for channel 1.

According to the present embodiment, a DMA expansion agent must signalits remaining active requests after a first request is serviced. Atprocess block 715, the DMA expansion agent deasserts its REQ# signal fortwo clock cycles prior to signaling its remaining request. At processblock 720, the PCI DMA expansion agent asserts its REQ# signal accordingto the serial channel passing protocol to request any remaining activetransactions. The request is granted at process block 725, and thetransaction completes at process block 730. If at process block 735 theDMA expansion agent still has outstanding active requests from its DMAagents, process block 715-730 are repeated until no active requestsremain, at which time the process ends at process block 740.

FIG. 8 is a flow chart showing a process for handling a situationwherein a DMA expansion agent that has signaled multiple requests tosystem I/O controller 25 has one of the requests go inactive prior toreceiving a grant signal for any of the active requests. At processblock 800, the DMA expansion agent signals that it has multiple activerequests by toggling its REQ# signal line as shown in FIG. 6. At processblock 805, prior to receiving a grant, the request of a first secondarybus agent goes inactive. At process block 810, the DMA expansion agentdrives its REQ# signal line inactive for one clock cycle. At processblock 815, the DMA expansion agent signals its remaining active requestor requests using the serial channel passing protocol shown in FIG. 6.The process ends at process block 820.

For example, if a DMA expansion agent has active requests for channels 1and 2, the DMA expansion agent signals both requests as active using theserial channel passing protocol. If the request for channel 1 goesinactive prior to the DMA expansion agent receiving an encoded GNT#signal from encode/decode logic 132, the DMA expansion agent deassertsits REQ# signal for one clock cycle and then transmits its request forchannel 2 using the serial channel passing protocol.

FIG. 9 is a flow chart showing a process for handling a situationwherein a DMA expansion agent having an outstanding request receives anew active request before receiving a grant from the system I/Ocontroller. At process block 900, the DMA expansion agent signals thatit has one or more requests. At process block 905, prior to the receiptof a grant signal, the DMA expansion agent detects a new active request.At process block 910, the DMA expansion agent drives its REQ# signalline inactive for one clock cycle, and the PCI DMA expansion agentsignals all of its active requests using the serial channel passingprotocol at process block 915. The process ends at process block 920.

FIG. 10 shows an alternative serial channel passing protocol whereineach primary bus agent may only request access to a single channel.Therefore, each DMA agent may only request access to one DMA channel Asshown, a requesting agent requests an access by encoding a channelrequest over four bus cycles. After the first bus cycle, three buscycles are provided wherein the requesting primary bus agent asserts ordeasserts its REQ# signal during each bus cycle to encode the channelrequest. After the fourth bus cycle, the REQ# signal of the requestingagent remains asserted as long as the request remains active. A requestis granted by merely asserting the appropriate GNT# signal. The decodingof the channel request may be that shown in FIG. 5. The encoded serialchannel passing protocol may be used by all primary bus agents,obviating the need for the REQ#/GNT# control registers shown in FIG. 4.One disadvantage of this alternative method is that it does not providefor DMA agents that request multiple channels.

DMA CYCLE PROTOCOLS

Once a DMA request is granted, DMA controller 135 controls the DMAtransfer. Thus, the requesting primary bus agent that has received thegrant is not actually granted control of the primary bus as a busmaster. DMA controller 135 supports DMA read transfers (memory to I/O),DMA write transfers (I/O to memory), and DMA verify transfers. DMAcontroller 135 also supports ISA master cycles. Each DMA read or writetransfer is a two phase transfer including an I/O phase and a memoryphase. During the I/O phase, DMA controller 135 causes data to be readfrom or written to a bus agent. During the memory phase, DMA controller135 causes data to be written to or read from system memory. The orderin which the I/O and memory phases are performed is determined by thetype of DMA transfer. A DMA verify transfer includes only an I/O phasecomprising an I/O read transaction.

The precise manner in which DMA transfers are performed is determined bythe transfer mode used by DMA controller 135. DMA controller 135supports the single transfer mode, the block transfer mode, the demandtransfer mode, and the cascade mode specified by the ISA systemarchitecture. Wherein DMA controller 135 implements ISA/EISA DMAprotocols, other DMA protocols may be used depending on the busarchitectures implemented by the secondary buses.

According to the single transfer mode, DMA controller 135 relinquishescontrol of primary bus 15 after each byte, word, or double word istransferred so that the processor 50 may have access to primary bus 15on a regular basis. The single transfer mode is implicitly supportedwhen a DMA agent immediately deasserts its REQ# signal after everytransfer, or when DMA controller 135 deasserts the appropriate DACK#signal after every transfer such that primary bus 130 deasserts the GNT#signal of the DMA agent. A DMA agent may deassert its REQ# signal inresponse to the requesting secondary bus agent deasserting its DREQ#signal or in response to detecting deassertion of the GNT# signal line.

According to the block transfer mode, a block of data of any size istransferred by DMA controller 135 performing multiple successive DMAtransfers. The block transfer mode may be implemented so long as primarybus arbiter 130 does not include a time-out mechanism that specifies amaximum time that a primary bus agent can own the primary bus. Accordingthe demand transfer mode, DMA controller 135 performs successive DMAtransfers as long as the granted DMA agent asserts its REQ# signal line.To signal that the DMA agent can no longer supply or accept data, theDMA agent or DMA expansion agent must deassert its REQ# signal line fortwo clock cycles.

Both the I/O phase and the memory phase of a DMA transfer are performedby primary bus interface logic 131 using normal primary bus read andwrite transactions in response to DMA controller 135. When primary bus15 is a PCI Local Bus, a DMA read transfer may include a PCI memory readtransaction for the memory phase followed by a PCI I/O write transactionfor the I/O phase. A DMA write transfer may include two 16-bit PCI I/Oread transactions for the I/O phase followed by a single 32-bit memoryread transaction for the memory phase. FIG. 11 shows a normal PCI readtransaction, and FIG. 12 shows a normal PCI write transaction.

For both PCI read and write transactions, multiplexed command/byteenable signal lines C/BE# 3:0! are used to indicate the PCI bus command(e.g., I/O read, I/O write, memory read, and memory write) during oneportion of a given transaction and to indicate the byte lanes for dataduring a subsequent portion of the transaction. Similarly, multiplexedaddress and data lines AD 31:0! are used to communicate the address tobe accessed by the transaction during one portion of the transaction andto carry the data for the transaction during subsequent portions of thetransaction. According to the present embodiment, the GNT# signal of theDMA agent must remain asserted until the last data phase of the I/Ophase of the DMA transfer.

As described above, the electrical interface between DMA controller 135and primary bus interface logic 131 includes several signals that arenormally coupled directly to requesting I/O devices, and many of thesesignals indicate the type of DMA cycle that is to occur. For example,the terminal count TC signal indicates whether the current data is thelast data of a block. A mechanism should be provided to "pass" pertinentDMA control signals to DMA agents.

According to the present embodiment, primary bus interface logic 131uses the address lines of the primary bus during the address portion ofa primary bus transaction to pass DMA control information to a DMAagent. The address lines of the primary bus are not required to pass avalid address during the I/O portion of a DMA transfer because a DMAagent also receives a grant signal that selects the DMA agent. Controlinformation is passed by setting the address lines to one of a pluralityof values that correspond to the address space of DMA controller 135.The DMA agent that detects an active grant signal decodes the value ofthe address lines to determine the control information. To properlyrecognize the initiation of the I/O portion of the DMA cycle, every DMAagent and DMA expansion agent must recognize the assertion of itscorresponding GNT# signal combined with the receipt of encoded DMAcontrol information as its command authorization to initiate a DMAaccess cycle.

The control information passed by primary bus interface logic 131includes information regarding whether a particular DMA cycle is anormal read or write cycle, a verify cycle, or a terminal count cycle.FIG. 13 shows an exemplary decoding of address line values to controlinformation wherein the address values are selected to correspond to theaddress space of DMA controller 135 such that no conflicts with otherdevices can occur. A normal I/O read or write cycle is signaled byindicating a normal PCI I/O read or write transaction as the bus commandand setting the address to a value of 00 h. A terminal count I/O read orwrite cycle is signaled by indicating a normal PCI I/O read or writetransaction as the bus command and setting the address to a value of 04h. A verify operation is signaled by indicating a normal I/O readoperation as the bus command and setting the address to a value of 0C0h. A verify with terminal count is signaled by indicating a normal PCII/O read transaction and setting the address to a value of 0C4h.

According to the PCI Local Bus standard, all PCI agents are double wordaligned and therefore are connected to all of the multiplexed addressand data lines AD 31:0!. The byte enable lines BE# are used to indicatewhich bytes of the multiplexed address and data lines AD 31:0! carrymeaningful data during the data phase of a bus transaction. According tothe present embodiment, DMA agents of the primary bus may be byte wide,word wide, or double word wide. FIG. 14 shows a possible alignment ofDMA agents with respect to the multiplexed address and data lines AD31:0!. FIG. 14 shows that a DMA agent that is a byte wide is coupled toAD 7:0!, a DMA agent that is a word wide is coupled to AD 15:0!, and aDMA agent that is double-word wide is coupled to AD 31:0!. FIG. 15 showsa decoding of the byte enable lines BE# 3:0! that corresponds to thealignment of DMA agents shown in FIG. 14. The byte enable lines BE# 3:0!are asserted as shown in FIG. 15 during the I/O phase of a DMA transferaccording to the data width of the DMA agent.

FIG. 16 shows an exemplary DMA write transfer according to a oneembodiment. The timing diagram is not to scale. As shown, a DMAexpansion agent signals a request using a serial channel passingprotocol, and encode/decode logic 132 of system I/O controller 25responds with a serial grant. The requested DMA transfer is a DMA writetransfer, and the DMA expansion agent is a 16-bit wide device. Toperform a 32-bit write to memory, two 16-bit I/O reads are performedduring the I/O phase of the DMA transfer, and a single 32-bit memorywrite is performed during the memory phase of the DMA transfer.

As shown, the first 16-bit I/O read occurs after the grant is received.During each of the 16-bit I/O read transactions, the address and datalines AD 31:0! initially carry an encoded control information value of"00h," which indicates a normal DMA I/O operation. While the address anddata lines carry the encoded control information, the command and byteenable lines C/BE# 3:0! carry a bus command value of "00h," whichindicates an I/O read. Therefore, a normal I/O read of the DMA expansionagent is to occur. The command and byte enable lines C/BE# 3:0!subsequently carry a value of "0Ch," which indicates that address anddata lines 0:15! carry valid data. The sixteen bits of the first I/Oread transaction are stored in buffer 137 in bit positions 0 to 15. Thesixteen bits of the second I/O read transaction are conveyed usingaddress and data lines AD 15:0!, but are stored in bit positions 16 to31. During the 32-bit memory write operation, the contents of buffer 137are placed on the address and data lines AD 31:0!, and all byte lanesare enabled. Thus, a 32-bit DMA write transfer may be accomplished.

In the foregoing specification the invention has been described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of the invention.The specification and drawings are, accordingly, to be regarded in anillustrative rather than restrictive sense.

What is claimed is:
 1. A computer system comprising:a processor; a localbus coupled to the processor; a direct memory access (DMA) agentconfigured to request direct access to a memory device; and a systeminput/output (I/O) controller coupled to the local bus, including: adirect memory access (DMA) controller; interface logic coupled to theDMA controller and configured to communicate over the local busaccording to a local bus protocol; a plurality of control/byte enablelines coupled to the interface logic wherein the control/byte enablelines carry control and byte enable information in a time multiplexedmanner; and a plurality of address lines coupled to the interface logic,including address lines that carry DMA control information from the DMAcontroller to the DMA agent through the interface logic, the controlinformation including a type of DMA cycle.
 2. The computer system ofclaim 1, wherein the type of DMA cycle includes:a normal read cycle; anormal write cycle; a verify cycle; and a terminal count cycle.
 3. Thecomputer system of claim 1, wherein the system I/O controller furthercomprises a primary bus arbiter coupled to the DMA controller andconfigured to arbitrate for the local bus on behalf of the DMA agent. 4.A system input/output (I/O) controller comprising:a direct memory access(DMA) controller; interface logic coupled to the DMA controller andconfigured to communicate over a local bus according to a local busprotocol; a plurality of control/byte enable lines coupled to theinterface logic wherein the control/byte enable lines carry control andbyte enable information in a time multiplexed manner; and a plurality ofaddress lines coupled to the interface logic, including address linesthat carry DMA control information from the DMA controller to a DMAagent through the interface logic, including a type of DMA cycle.
 5. Thesystem I/O controller of claim 4, further comprising a primary busarbiter coupled to the DMA controller and configured to arbitrate forthe local bus on behalf of the DMA agent.
 6. The system I/O controllerof claim 4, wherein the type of DMA cycle includes:a normal read cycle;a normal write cycle; a verify cycle; and a terminal count cycle.
 7. Thesystem I/O controller of claim 4, further comprising encode/decode logiccoupled to the DMA controller and configured to receive encoded requestsfor DMA operations from the DMA agent and to transmit grant signals tothe DMA agent.
 8. A method for controlling direct access to a memorydevice of a computer system by a direct memory access (DMA) agent,comprising the steps of: receiving a DMA request over a local bus fromthe DMA agent according to a serial protocol;transmitting a grant signalover the local bus to the DMA agent granting the DMA request; performinga memory phase of the DMA transaction, including: transmitting addressinformation via address/data lines of the local bus; transmitting localbus command information via control/byte enable lines of the local bus;and transferring data between the memory device and a data buffer viathe address/data lines; and performing an input/output (I/O) phase ofthe DMA transaction, including: transmitting byte lane information viathe control/byte enable lines; and transmitting a signal to convey DMAcontrol information to the DMA agent wherein the signal is encoded onthe address/data lines.
 9. The method of claim 8, wherein the DMAcontrol information comprises a DMA cycle type, including:a normal readcycle; a normal write cycle; a verify cycle; and a terminal count cycle.